Design of a real-time face detection parallel architecture using high-level synthesis

Category

Journal Article

Authors

Farrugia, N., Mamalet, F., Roux, S., Yang, F., Paindavoine, M.

Year

2008

Title

Design of a real-time face detection parallel architecture using high-level synthesis

Journal / book / conference

EURASIP Journal on Embedded Systems

Abstract

We describe a High-Level Synthesis implementation of a parallel architecture for face detection. The chosen face detection method is the well-known Convolutional Face Finder (CFF) algorithm, which consists of a pipeline of convolution operations.We rely on dataflow modelling of the algorithm and we use a high-level synthesis tool in order to specify the local dataflows of our Processing Element (PE), by describing in C language inter-PE communication, fine scheduling of the successive convolutions, and memory distribution and bandwidth. Using this approach, we explore several implementation alternatives in order to find a compromise between processing speed and area of the PE. We then build a parallel architecture composed of a PE ring and a FIFO memory, which constitutes a generic architecture capable of processing images of different sizes. A ring of 25 PEs running at 80MHz is able to process 127 QVGA images per second or 35 VGA images per second.

Volume

2008

Pages

1-9

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