The eISP a low-power and tiny silicon footprint programmable video architecture

Authors

Thevenin, M., Paindavoine, M., Letellier, L., Schmit, R.

Year

2010

Title

The eISP a low-power and tiny silicon footprint programmable video architecture

Journal / book / conference

Journal of Real-Time Image Processing

Abstract

CMOS sensors are now more and more frequently integrated into popular consumer products. Images from these sensors thus need to be digitally processed for display purposes. To do so, CMOS sensors are associated with dedicated components that keep power consumption low. However, use of dedicated components limits hardware flexibility and prevents updating of image processing algorithms. This paper describes the eISP, a programmable processing architecture that combines enough computational efficiency for 1080p HD video with silicon area and power characteristics suitable for the next generation of mobile phones (lower than 1 mm2 and 500 mW in TSMC 65 nm).

Issue

Special

Pages

1-14

Keywords

Embedded programmable image video processor Low power CMOS High definition VLIW Video pipe

‹ Back

LEAD